1. Field of the Invention
The present invention relates generally to capacitors formed within integrated circuits. More particularly, the present invention relates to low voltage coefficient polysilicon capacitors formed within integrated circuits.
2. Description of the Related Art
In addition to resistors, transistors and diodes, integrated circuits of various types typically also often have capacitors formed within their fabrications. Capacitors formed within analog integrated circuit fabrications typically assure proper operation of those analog integrated circuits. Capacitors formed within digital integrated circuits typically provide charge storage locations for individual bits of digital data stored within those digital integrated circuits.
A common type of capacitor typically although not exclusively formed within an analog integrated circuit is a double layer polysilicon capacitor. Double layer polysilicon capacitors are formed from two substantially planar conductive polysilicon electrodes separated by a dielectric layer. Double layer polysilicon capacitors provide several advantages when used within integrated circuits. For example, double layer polysilicon capacitors may easily be formed within several locations within an integrated circuit. In addition, methods for forming double layer polysilicon capacitors typically provide efficient manufacturing processes since other portions of the blanket polysilicon layers from which are formed the two polysilicon electrodes within a double layer polysilicon capacitor may be employed in forming other polysilicon structures within the integrated circuit within which is formed the double layer polysilicon capacitor. Commonly, portions of one or both of the two polysilicon layers are employed in simultaneously forming: (1) polysilicon or polycide (polysilicon/metal silicide stack) gate electrodes within Field Effect Transistors (FETs), and/or (2) polysilicon or polycide contacts within bipolar transistor electrodes, which Field Effect Transistors and/or bipolar transistors are formed within the integrated circuit within which is formed the double layer polysilicon capacitor.
When forming double layer polysilicon capacitor electrodes simultaneously from polysilicon layers which are employed in forming polysilicon or polycide (polysilicon/metal silicide stack) gate electrodes within Field Effect Transistors (FETs), it is common in the art to encounter an integrated circuit structure similar to the integrated circuit structure generally illustrated by FIG. 1. Such integrated circuit structures are disclosed by Natsume in U.S. Pat. No. 5,356,826. Shown in FIG. 1 is a semiconductor substrate 10 within and upon whose surface is formed isolation regions 12a and 12b which define the active region of the semiconductor substrate 10. Formed upon the active region of the semiconductor substrate 10 is a polycide gate electrode formed upon a gate oxide layer 13. The polycide gate electrode is formed from a patterned first polysilicon layer 14a upon which resides a patterned metal silicide layer 16a. The patterned metal silicide layer 16a typically provides a low contact resistance to the polycide gate electrode. The patterned first polysilicon layer 14a and the patterned metal silicide layer 16a are patterned from the same blanket first polysilicon layer and blanket metal silicide layer which simultaneously form the patterned first polysilicon layer 14b and the patterned metal silicide layer 16b. Together, the patterned first polysilicon layer 14b and the patterned metal silicide layer 16b form the first polysilicon electrode of a double layer polysilicon capacitor which resides upon the isolation region 12b. Formed upon the patterned metal silicide layer 16b is a patterned insulator layer 18, and formed upon the patterned insulator layer 18 is a patterned second polysilicon layer 20. The patterned second polysilicon layer 20 forms the second polysilicon electrode of the double layer polysilicon capacitor.
Although the integrated circuit structure illustrated in FIG. 1 provides an operational double layer polysilicon capacitor, the double layer polysilicon capacitor so formed often suffers from a high voltage coefficient. The voltage coefficient of a capacitor is a parameter which measures the space-charge layer capacitance within the electrodes of a capacitor, in addition to the capacitance contribution attributable to the dielectric layer which separates the electrodes of the capacitor. In order to assure optimal performance of integrated circuits having double layer polysilicon capacitors formed therein, it is often desirable to maintain low voltage coefficients of those double layer polysilicon capacitors. It is thus in part towards the goal of maintaining low voltage coefficient double layer polysilicon capacitors that the present invention is directed.
Also known within the art of integrated circuits whose structures are similar to the integrated circuit illustrated in FIG. 1 is the phenomenon of delamination between the patterned metal silicide layer 16a and the patterned first polysilicon layer 14a, and the patterned metal silicide layer 16b and the patterned first polysilicon layer 14b. Delamination between those pairs of patterned metal silicide layers and patterned first polysilicon layers is more likely to occur as the patterned first polysilicon layer 14a and the patterned first polysilicon layer 14b become more conductive through incorporation of high dopant concentrations. Thus, it is also towards the goal of forming double layer polysilicon capacitors having at least one low contact resistance electrode with limited susceptibility to delamination that the present invention is additionally directed.
Although not necessarily directly pertinent to the goals of the present invention, various additional aspects of the methods and materials through which double layer polysilicon capacitors may be formed within integrated circuits are disclosed in the art. For example, Chi, in U.S. Pat. No. 5,173,437 discloses a two-step method employing two photolithographic masks for forming a double layer polysilicon capacitor, adjoining the edges of the lower polysilicon electrode of which are absent polysilicon stringers which otherwise might short from the polysilicon electrodes of the double layer polysilicon capacitor to other conductive elements within the integrated circuit within which is formed the double layer polysilicon capacitor.
Desirable in the art are double layer polysilicon capacitors and methods for forming those double layer polysilicon capacitors, which double layer polysilicon capacitors exhibit low voltage coefficients, and at least one of the electrodes of which double layer polysilicon capacitors has a low contact resistance and a limited susceptibility to delamination.